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36-mbit qdr-ii? sram 2-word burst architecture cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05615 rev. *d revised july 09, 2007 features ? separate independent read and write data ports ? supports concurrent transactions ? 250-mhz clock for high bandwidth ? 2-word burst on all accesses ? double data rate (ddr) interfaces on both read and write ports (data transferred at 500 mhz) @ 250 mhz ? two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only ? two input clocks for output data (c and c ) to minimize clock skew and flight-time mismatches ? echo clocks (cq and cq ) simplify data capture in high-speed systems ? single multiplexed address input bus latches address inputs for both read and write ports ? separate port selects for depth expansion ? synchronous internally self timed writes ? available in x8, x9, x18, and x36 configurations ? full data coherency, providing most current data ? core v dd = 1.8v (0.1v); io v ddq = 1.4v to v dd ? available in 165-ball fbga package (15 x 17 x 1.4 mm) ? offered in both pb-free and non pb-free packages ? variable drive hstl output buffers ? jtag 1149.1 compatib le test access port ? delay lock loop (dll) for accurate data placement configurations cy7c1410av18 ? 4m x 8 CY7C1425AV18 ? 4m x 9 cy7c1412av18 ? 2m x 18 cy7c1414av18 ? 1m x 36 functional description the cy7c1410av18, CY7C1425AV18, cy7c1412av18, and cy7c1414av18 are 1.8v synchronous pipelined srams, equipped with qdr?-ii archit ecture. qdr-ii architecture consists of two separate port s to access the memory array. the read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations. qdr-ii architecture has separate data inputs and data outputs to completely eliminate the need to ?turn-around? the data bus required with common io devices. access to each por t is accomplished through a common address bus. the read address is latched on the rising edge of the k clock and the write address is latched on the rising edge of the k clock. accesses to the qdr-ii read and write ports are completely independent of one another. in order to maximize data throughput, both read and write ports are equipped with double data rate (ddr) interfaces. each address location is associated with two 8-bit words (cy7c1410av18) or 9-bit words (CY7C1425AV18) or 18-bit words (cy7c1412av18) or 36-bit words (cy7c1414av18) that burst sequentially into or out of the device. while data can be transferred into and out of the device on every rising edge of both input clocks (k and k and c and c ), memory bandwidth is maximized while simplifying system design by eliminating bus ?turn-arounds.? depth expansion is accomplished with port selects for each port. port selects allow each port to operate independently. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c (or k or k in a single clock domain) input clocks. writes are conducted with on-chip synchronous self timed write circuitry. selection guide 250 mhz 200 mhz 167 mhz unit maximum operating frequency 250 200 167 mhz maximum operating current 1065 870 740 ma
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 2 of 25 logic block diagram (cy7c1410av18) clk a (20:0) gen. k k control logic address register d [7:0] read add. decode read data reg. rps wps q [7:0] control logic address register reg. reg. reg. 8 21 8 16 8 nws [1:0] v ref write add. decode 8 a (20:0) 21 c c 8 2m x 8 array 2m x 8 array write reg write reg cq cq 8 doff logic block diagram (CY7C1425AV18) clk a (20:0) gen. k k control logic address register d [8:0] read add. decode read data reg. rps wps q [8:0] control logic address register reg. reg. reg. 9 21 9 18 9 bws [0] v ref write add. decode 9 a (20:0) 21 c c 9 2m x 9 array 2m x 9 array write reg write reg cq cq 9 doff
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 3 of 25 logic block diagram (cy7c1412av18) clk a (19:0) gen. k k control logic address register d [17:0] read add. decode read data reg. rps wps q [17:0] control logic address register reg. reg. reg. 18 20 18 36 18 bws [1:0] v ref write add. decode 18 a (19:0) 20 c c 18 1m x 18 array 1m x 18 array write reg write reg cq cq 18 doff logic block diagram (cy7c1414av18) clk a (18:0) gen. k k control logic address register d [35:0] read add. decode read data reg. rps wps q [35:0] control logic address register reg. reg. reg. 36 19 36 72 36 bws [3:0] v ref write add. decode 36 a (18:0) 19 c c 36 512k x 36 array 512k x 36 array write reg write reg cq cq 36 doff
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 4 of 25 pin configurations cy7c1410av18 (4m x 8) 23 4567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a nws 1 k wps nc/144m nc nc nc nc nc tdo nc nc d5 nc nc nc tck nc nc a nc/288m k nws 0 v ss aaa nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd q4 nc v ddq nc nc nc nc q7 a v ddq v ss v ddq v dd v dd q5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d4 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc q6 nc d7 d6 v dd a 891011 nc aa rps cq a nc nc q3 v ss nc nc d3 nc v ss nc q2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d1 v ddq nc q1 nc v ddq v ddq nc v ss nc d0 nc tdi tms v ss a nc a nc d2 nc zq nc q0 nc nc nc nc a 165-ball fbga (15 x 17 x 1.4 mm) pinout CY7C1425AV18 (4m x 9) 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m anck wps nc/144m nc nc nc nc nc tdo nc nc d6 nc nc nc tck nc nc a nc/288m k bws 0 v ss aaa nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd q5 nc v ddq nc nc nc nc q8 a v ddq v ss v ddq v dd v dd q6 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d5 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc q7 nc d8 d7 v dd a 891011 q0 aa rps cq a nc nc q4 v ss nc nc d4 nc v ss nc q3 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d2 v ddq nc q2 nc v ddq v ddq nc v ss nc d1 nc tdi tms v ss a nc a nc d3 nc zq nc q1 nc nc d0 nc a
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 5 of 25 pin configurations (continued) cy7c1412av18 (2m x 18) 234 56 7 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/144m a bws 1 k wps nc/288m q9 d9 nc nc nc tdo nc nc d13 nc nc nc tck nc d10 a nc k bws 0 v ss aaa q10 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q11 d12 v ddq d14 q14 d16 q16 q17 a v ddq v ss v ddq v dd v dd q13 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d11 v ss nc v ss q12 nc v ref v ss v dd v ss v ss a v ss c nc q15 nc d17 d15 v dd a 891011 q0 a nc/72m rps cq a nc nc q8 v ss nc q7 d8 nc v ss nc q6 d5 nc nc v ref nc q3 v ddq nc v ddq nc q5 v ddq v ddq v ddq d4 v ddq nc q4 nc v ddq v ddq nc v ss nc d2 nc tdi tms v ss a nc a d7 d6 nc zq d3 q2 d1 q1 d0 nc a 165-ball fbga (15 x 17 x 1.4 mm) pinout 23 4 567 1 a b c d e f g h j k l m n p r a cq q27 d27 d28 d34 doff q33 nc/288m nc/72m bws 2 k wps bws 1 q18 d18 q30 d31 d33 tdo q28 d29 d22 d32 q34 q31 tck d35 d19 a bws 3 k bws 0 v ss aaa q19 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q20 d21 v ddq d23 q23 d25 q25 q26 a v ddq v ss v ddq v dd v dd q22 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d20 v ss q29 v ss q21 d30 v ref v ss v dd v ss v ss a v ss c q32 q24 q35 d26 d24 v dd a 891011 q0 a nc/144m rps cq a d17 q17 q8 v ss d16 q7 d8 q16 v ss d15 q6 d5 d9 q14 v ref q11 q3 v ddq q15 v ddq d14 q5 v ddq vddq v ddq d4 v ddq d12 q4 q12 v ddq v ddq d11 v ss d10 d2 q10 tdi tms v ss a q9 a d7 d6 d13 zq d3 q2 d1 q1 d0 q13 a cy7c1414av18 (1m x 36)
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 6 of 25 pin definitions pin name io pin description d [x:0] input- synchronous data input signals, sampled on the rising edge of k and k clocks during valid write operations . cy7c1410av18 - d [7:0] CY7C1425AV18 - d [8:0] cy7c1412av18 - d [17:0] cy7c1414av18 - d [35:0] wps input- synchronous write port select, active low . sampled on the rising edge of the k clock. when asserted active, a write operation is initia ted. deasserting deselects the write port. deselecting the write port causes d [x:0] to be ignored. nws 0 ,nws 1 nibble write select 0, 1 ? active low. (cy7c1410av18 only) sampled on the rising edge of the k and k clocks during write operat ions. used to select wh ich nibble is written into the device during the current portion of the write operations .nibbles not written remain unaltered. nws 0 controls d [3:0] and nws 1 controls d [7:4] . all nibble write selects are sampled on the same edge as the data. deselecting a nibble write select causes the corresponding nibble of data to be ignored and not written into the device. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2 and 3 ? active low . sampled on the rising edge of the k and k clocks during write operations. used to sele ct which byte is writ ten into the device during the current portion of the write operations. bytes not written remain unaltered. CY7C1425AV18 ? bws 0 controls d [8:0] cy7c1412av18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] . cy7c1414av18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] ,bws 2 controls d [26:18] and bws 3 controls d [35:27]. all the byte write selects are sampled on the same edge as the data. deselecting a byte write select causes the corresponding byte of data to be ignored and not written into the device. a input- synchronous address inputs. sampled on the rising edge of the k (read address) and k (write address) clocks during active read and write operations. these address inputs are multiplexed for both read and write operations. in ternally, the device is organized as 4m x 8 (2 arrays each of 2m x 8) for cy7c1410av18, 4m x 9 (2 arrays each of 2m x 9) for CY7C1425AV18, 2m x 18 (2 arrays each of 1m x 18) for cy7c1412av18 and 1m x 36 (2 arrays each of 512k x 36) for cy7c1414av18. therefore, only 21 address inputs are needed to access the entire memory array of cy7c1410av18 and CY7C1425AV18, 20 address inputs for cy7c1412av18 and 19 address inputs for cy7c1414av18. these inputs are ignored when the appr opriate port is deselected. q [x:0] outputs- synchronous data output signals . these pins drive out the request ed data during a read operation. valid data is driven out on the ri sing edge of both the c and c clocks during read operations or k and k when in single clock mode. when the read port is deselected, q [x:0] are automatically tri-stated. cy7c1410av18 ? q [7:0] CY7C1425AV18 ? q [8:0] cy7c1412av18 ? q [17:0] cy7c1414av18 ? q [35:0] rps input- synchronous read port select, active low . sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting causes the read port to be deselected. when deselec ted, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the c clock. each read access consists of a burst of two sequential transfers. c input-clock positive input clo ck for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. c input-clock negative input clock for output data . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details.
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 7 of 25 functional overview the cy7c1410av18, CY7C1425AV18, cy7c1412av18 and cy7c1414av18 are synchronous pipelined burst srams equipped with both a read port and a write port. the read port is dedicated to read operations and the write port is dedicated to write operations. data flows into the sram through the write port and out through the read port. these devices multiplex the address inputs in order to minimize the number of address pins required. by having separate read and write ports, the qdr-ii comp letely eliminates the need to ?turn-around? the data bus and avoids any possible data contention, thereby simplifying system design. each access consists of two 8-bit data transfers in the case of cy7c1410av18, two 9-bit data transfers in the case of CY7C1425AV18,two 18-bit data transfers in the case of cy7c1412av18 and two 36-bit data transfers in the case of cy7c1414av18, in one clock cycle. accesses for both ports are initiated on the rising edge of the positive input clock (k). all synchronous input timings are referenced from the rising edge of the input clocks (k and k ) and all output timings are referenced to the rising edge of output clocks (c and c or k and k when in single clock mode). all synchronous data inputs (d [x:0] ) inputs pass through input registers controlled by t he input clocks (k and k ). all synchronous data outputs (q [x:0] ) outputs pass through output registers controlled by the risi ng edge of the output clocks (c and c or k and k when in single clock mode). all synchronous control (rps , wps , bws [x:0] ) inputs pass through input registers controlled by the rising edge of the input clocks (k and k ). cy7c1412av18 is described in the following sections. the same basic descriptions apply to cy7c1410av18, CY7C1425AV18, and cy7c1414av18. k input-clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input-clock negative input clock input . k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] when in single clock mode. cq echo clock cq is referenced with respect to c . this is a free running clock and is synchronized to the input clock for output data (c) of th e qdr-ii. in the single clock mode, cq is generated with respect to k. the timings for the echo clocks are shown in the ac timing table. cq echo clock cq is referenced with respect to c . this is a free running clock and is synchronized to the input clock for output data (c ) of the qdr-ii. in the single clock mode, cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table. zq input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. cq, cq , and q [x:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternately, this pin can be connected directly to v ddq , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. doff input dll turn off, active low . connecting this pin to ground turns off the dll inside the device. the timings in the dll turned off operat ion is different from those listed in this data sheet. tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc n/a not connected to the die . can be tied to any voltage level. nc/72m n/a not connected to the die . can be tied to any voltage level. nc/144m n/a not connected to the die . can be tied to any voltage level. nc/288m n/a not connected to the die . can be tied to any voltage level. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name io pin description
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 8 of 25 read operations the cy7c1412av18 is organized internally as 2 arrays of 1mx18. accesses are completed in a burst of two sequential 18-bit data words. read operati ons are initiated by asserting rps active at the rising edge of the positive input clock (k). the address is latched on the rising edge of the k clock. the address presented to address inputs is stored in the read address register. following the next k clock rise the corre- sponding lowest order 18-bit wo rd of data is driven onto the q [17:0] using c as the output timing reference. on the subse- quent rising edge of c, the next 18 -bit data word is driven onto the q [17:0] . the requested data is valid 0.45 ns from the rising edge of the output clock (c and c or k and k when in single clock mode). synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the output clocks (c/c ). this allows for a seamless transition between devices without the insertion of wait states in a depth expanded memory. write operations write operations are init iated by asserting wps active at the rising edge of the positive input clock (k). on the same k clock rise, the data presented to d [17:0] is latched and stored into the lower 18-bit write data register provided bws [1:0] are both asserted active. on the subsequent rising edge of the negative input clock (k ), the address is latched and the infor- mation presented to d [17:0] is stored into the write data register provided bws [1:0] are both asserted active. the 36 bits of data are then written into the memory array at the specified location. when deselecte d, the write port ignores all inputs after the pending write operations have been completed. byte write operations byte write operations are supported by the cy7c1412av18. a write operation is initiated as described in the write opera- tions section above. the bytes that are written are determined by bws 0 and bws 1 , which are sampled with each 18-bit data word. asserting the appropriate byte write select input during the data portion of a write allows the data being presented to be latched and written into the device. deasserting the byte write select input during the data portion of a write allows the data stored in the device for th at byte to remain unaltered. this feature can be used to simplify read/modify/write operations to a byte write operation. single clock mode the cy7c1412av18 can be used with a single clock that controls both the input and output registers. in this mode, the device recognizes only a single pair of input clocks (k and k ) that control both the input and ou tput registers. this operation is identical to the operation if the device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use th is mode of operation, the user must tie c and c high at power on. this function is a strap option and not alterable during device operation. concurrent transactions the read and write ports on the cy7c1412av18 operate completely independently of one another. while each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the trans- action on the other port. also, reads and writes can be started in the same clock cycl e. if the ports access the same location at the same time, the sram delivers the most recent infor- mation associated with the specified address location. this includes forwarding data from a write cycle that was initiated on the previous k clock rise. depth expansion the cy7c1412av18 has a port select input for each port. this allows for easy depth expansion. both port selects are sampled on the rising edge of the positive input clock only (k). each port select input can deselect the specified port. deselecting a port does not affect the other port. all pending transactions (read and write) are completed prior to the device being deselected. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the va lue of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq = 1.5v.the output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on the qdr-ii to simplify data capture on high-speed system s. two echo clocks are generated by the qdr-ii. cq is referenced with respect to c and cq is referenced with respect to c . these are free-running clocks and are syn chronized to t he output clock (c/c ) of the qdr-ii. in the singl e clock mode, cq is generated with respect to k and cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table. dll these chips use a delay lock loop (dll) that is designed to function between 80 mhz and the specified maximum clock frequency. during power up, when the doff is tied high, the dll gets locked after 1024 cycles of stable clock. the dll can also be reset by slowing or stopping the input clock k and k for a minimum of 30 ns. however, it is not necessary for the dll to be specifically reset in order to lock the dll to the desired frequency. the dll automatically locks 1024 clock cycles after a stable clock is presented.the dll may be disabled by applying ground to the doff pin. for information refer to the application no te ?dll considerations in qdrii/ddrii/qdrii+/ddrii+?.
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 9 of 25 application example [1] truth table [2, 3, 4, 5, 6, 7] operation k rps wps dq dq write cycle: load address on the rising edge of k clock; input write data on k and k rising edges. l-h x l d(a + 0) at k(t) d(a + 1) at k (t) read cycle: load address on the rising edge of k clock; wait one and a half cycle; read data on c and c rising edges. l-h l x q(a + 0) at c (t + 1) q(a + 1) at c(t + 2) nop: no operation l-h h h d = x q = high-z d = x q = high-z standby: clock stopped stopped x x previous state previous state write cycle descriptions (cy7c1410av18 and cy7c1412av18) [2, 8] bws 0 / nws 0 bws 1 / nws 1 kk comments l l l-h ? during the data portion of a write sequence : cy7c1410av18 ? both nibbles (d [7:0] ) are written into the device, cy7c1412av18 ? both bytes (d [17:0] ) are written into the device. l l ? l-h during the data portion of a write sequence : cy7c1410av18 ? both nibbles (d [7:0] ) are written into the device, cy7c1412av18 ? both bytes (d [17:0] ) are written into the device. l h l-h ? during the data portion of a write sequence : cy7c1410av18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] remains unaltered, cy7c1412av18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] remains unaltered. notes: 1. the above application shows four qdr-ii being used. 2. x = ?don't care,? h = logic high, l= logic low, represents rising edge. 3. device powers up deselected and the outputs in a tri-state condition. 4. ?a? represents address location latched by the devices when transaction was initiated. a + 00, a + 01 represents the internal address sequence in the burst. 5. ?t? represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles re spectively succeeding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 7. it is recommended that k = k and c = c = high when clock is stopped. this is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. assumes a write cycle was initiated according to the write port cycle description truth table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 and bws 3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. vt = vddq/2 cc# d a k cc# d a k bus master (cpu or asic) sram #1 sram #4 data in data out address rps# wps# bws# source k source k# delayed k delayed k# r = 50 ??? r = 250 ??? r = 250 ??? r p s # w p s # b w s # r p s # w p s # b w s # vt vt vt r r r zq cq/cq# q k# zq cq/cq# q k# clkin/clkin#
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 10 of 25 l h ? l-h during the data portion of a write sequence : cy7c1410av18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] remains unaltered, cy7c1412av18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] remains unaltered. h l l-h ? during the data portion of a write sequence : cy7c1410av18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] remains unaltered, cy7c1412av18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] remains unaltered. h l ? l-h during the data portion of a write sequence : cy7c1410av18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] remains unaltered, cy7c1412av18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] remains unaltered. h h l-h ? no data is written into the devices during this portion of a write operation. h h ? l-h no data is written into the devices during this portion of a write operation. write cycle descriptions (cy7c1414av18) [2, 8] bws 0 bws 1 bws 2 bws 3 kk comments l l l l l-h ? during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l l l l ? l-h during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l-h ? during the data portion of a wr ite sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. l h h h ? l-h during the data portion of a wr ite sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] remains unaltered. h l h h l-h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h l h h ? l-h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] remains unaltered. h h l h l-h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h l h ? l-h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] remains unaltered. h h h l l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h l ? l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] remains unaltered. h h h h l-h ? no data is written into the device during this portion of a write operation. h h h h ? l-h no data is written into the device during this portion of a write operation. write cycle descriptions (CY7C1425AV18) bws 0 kk comments l l-h ? during the data portion of a write sequence : CY7C1425AV18 - the single byte (d[8 :0]) is written into the device l ? l-h during the data portion of a write sequence : CY7C1425AV18 - the single byte (d[8 :0]) is written into the device h l-h ? no data is written into the devices during this portion of a write operation. h ? l-h no data is written into the devices during this portion of a write operation. write cycle descriptions (cy7c1410av18 and cy7c1412av18) (continued) [2, 8] bws 0 / nws 0 bws 1 / nws 1 kk comments
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 11 of 25 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard #1149.1-1900. the tap operates using jedec standard 1.8v io logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull up resistor. tdo must be left unconnected. upon power up, the device is up in a reset state which does not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is ac tive depending upon the current state of the tap state machine (see instruction codes). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (vdd) for five rising edges of tck. this rese t does not affect the operation of the sram and may be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected betw een the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register s. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in tap controller block diagram. upon power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. seve ral no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction code table. three of these instructions are listed as reserved and must not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction afte r it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr st ate. the idcode instruction
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 12 of 25 is loaded into the instruction register upon power up or whenever the tap controller is supplied a test logic reset state. sample z the sample z instruction caus es the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the next command is supplied during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructi ons are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the captur e-dr state, an input or output undergoes a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that is captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture setup plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sampl e/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the preloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system out put pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that t he tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #108. when this scan cell, called the ?extest output bus tri-state,? is latched into the preload register during the ?update-dr? state in the tap contro ller, it directly controls the state of the output (q-bus) pi ns, when the extest is entered as the current instruction. when high, it enables the output buffers to drive the output bus. when low, this bit places the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? stat e. during ?update-dr?, the value loaded into that shift-register cell latches into the preload register. when the extest instruction is entered, this bit directly controls th e output q-bus pins. note that this bit is pre-set low to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 13 of 25 note: 9. the 0/1 next to each state represents the value at tms at the rising edge of tck. tap controller state diagram [9] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 14 of 25 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range [15, 18, 10] parameter description test conditions min max unit v oh1 output high voltage i oh = ? 2.0 ma 1.4 v v oh2 output high voltage i oh = ? 100 a1.6 v v ol1 output low voltage i ol = 2.0 ma 0.4 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 0.65v dd v dd + 0.3 v v il input low voltage ?0.3 0.35v dd v i x input and output load current gnd v i v dd ? 55 a note: 10. these characteristic pertain to the tap inputs (tms, tck, tdi and tdo). parallel load levels are specified in the electrical characteristics table.
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 15 of 25 tap ac switching characteristics over the operating range [11, 12] parameter description min max unit t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high 20 ns t tl tck clock low 20 ns setup times t tmss tms setup to tck clock rise 5 ns t tdis tdi setup to tck clock rise 5 ns t cs capture setup to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns output times t tdov tck clock low to tdo valid 10 ns t tdox tck clock low to tdo invalid 0 ns tap timing and test conditions [12] notes: 11. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 12. test conditions are specified using th e load in tap ac test conditions. t r /t f = 1 ns. (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9v 50 ? 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data-in tdi test data-out t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdov t tdox tdo
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 16 of 25 identification register definitions instruction field value description cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 revision number (31:29) 000 000 000 000 version number. cypress device id (28:12) 11010011010000111 11010011010001111 11010011010010111 11010011010100111 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 00000110100 unique identifi- cation of sram vendor. id register presence (0) 1 1 1 1 indicates the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan cells 109 instruction codes instruction code description extest 000 captures the input/output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/output co ntents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the i nput/output ring contents. plac es the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation.
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 17 of 25 boundary scan order bit # bump id bit # bump id bit # bump id bit # bump id 0 6r 28 10g 56 6a 84 1j 16p 29 9g 57 5b 85 2j 2 6n 30 11f 58 5a 86 3k 3 7p 31 11g 59 4a 87 3j 47n329f605c882k 5 7r 33 10f 61 4b 89 1k 6 8r 34 11e 62 3a 90 2l 7 8p 35 10e 63 2a 91 3l 8 9r 36 10d 64 1a 92 1m 9 11p 37 9e 65 2b 93 1l 10 10p 38 10c 66 3b 94 3n 11 10n 39 11d 67 1c 95 3m 12 9p 40 9c 68 1b 96 1n 13 10m 41 9d 69 3d 97 2m 14 11n 42 11b 70 3c 98 3p 15 9m 43 11c 71 1d 99 2n 16 9n 44 9b 72 2c 100 2p 17 11l 45 10b 73 3e 101 1p 18 11m 46 11a 74 2d 102 3r 19 9l 47 10a 75 2e 103 4r 20 10l 48 9a 76 1e 104 4p 21 11k 49 8b 77 2f 105 5p 22 10k 50 7c 78 3f 106 5n 23 9j 51 6c 79 1g 107 5r 24 9k 52 8a 80 1f 108 internal 25 10j 53 7a 81 3g 26 11j 54 7b 82 2g 27 11h 55 6b 83 1h
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 18 of 25 power up sequence in qdr-ii sram [13, 14] qdr-ii srams must be powered up and initialized in a predefined manner to prevent undefined operations. power up sequence ? apply power and drive doff low (all other inputs can be high or low) ?apply v dd before v ddq ?apply v ddq before v ref or at the same time as v ref ? after the power and clock (k, k , c, c ) are stable take doff high ? the additional 1024 cycles of clocks are required for the dll to lock. dll constraints ? dll uses either k or c clock as its synchronizing input.the input must have low phase jitter, which is specified as t kc var . ? the dll functions at frequencies down to 80mhz. ? if the input clock is unstable and the dll is enabled, then the dll may lock to an incorrect frequency, causing unstable sram behavior . notes: 13. it is recommended that the doff pin be pulled high via a pull up resistor of 1 kohm. 14. during power up, when the doff is tied high, the dll gets locked af ter 1024 cycles of stable clock. power up waveforms > 1024 stable clock start normal operation doff stabl e (< +/- 0.1v dc per 50ns ) fix high (or tied to v ddq ) k k ddq dd v v / ddq dd v v / clock start ( clock starts after stable ) ddq dd v v / ~ ~ ~ ~ unstable clock
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 19 of 25 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. .... ??55c to +125c supply voltage on v dd relative to gnd........ ?0.5v to +2.9v supply voltage on v ddq relative to gnd ...... ?0.5v to +v dd dc voltage applied to outputs in high-z state .................................... ?0.5v to v ddq + 0.3v dc input voltage [18] ............................... ?0.5v to v dd + 0.3v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (mil-std-883, method 3015) latch up current.................................................... > 200 ma operating range range ambient temperature (t a )v dd [19] v ddq [19] com?l 0c to +70c 1.8 0.1v 1.4v to v dd ind?l ?40c to +85c electrical characteristics over the operating range [15, 19] dc electrical ch aracteristics over the operating range parameter description test conditions min typ max unit v dd power supply voltage 1.7 1.8 1.9 v v ddq io supply voltage 1.4 1.5 v dd v v oh output high voltage note 16 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v ol output low voltage note 17 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ? 0.1 ma, nominal impedance v ddq ? 0.2 v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss 0.2 v v ih input high voltage [18] v ref + 0.1 v ddq +0.3 v v il input low voltage [18] ?0.3 v ref ? 0.1 v i x input leakage current gnd v i v ddq ? 55 a i oz output leakage current gnd v i v ddq, output disabled ? 55 a v ref input reference voltage [20] typical value = 0.75v 0.68 0.75 0.95 v i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 167 mhz 740 ma 200 mhz 870 ma 250 mhz 1065 ma i sb1 automatic power down current max. v dd , both ports deselected, v in v ih or v in v il , f = f max = 1/t cyc, inputs static 167 mhz 270 ma 200 mhz 300 ma 250 mhz 350 ma ac input requirements over the operating range parameter description test conditions min typ max unit v ih input high (logic 1) voltage v ref + 0.2 ? ? v v il input low (logic 0) voltage ? ? v ref ? 0.2 v capacitance [21] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 1.8v v ddq = 1.5v 5pf c clk clock input capacitance 4 pf c o output capacitance 5 pf notes: 15. all voltage referenced to ground. 16. output are impedance controlled. i oh = ?(v ddq /2)/(rq/5) for values of 175 ? <= rq <= 350 ? s. 17. output are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? <= rq <= 350 ? . 18. overshoot: v ih (ac) < v ddq +0.85v (pulse width less than t cyc /2), undershoot: v il (ac) > ?1.5v (pulse width less than t cyc /2). 19. power up: assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . 20. v ref (min.) = 0.68v or 0.46v ddq , whichever is larger, v ref (max.) = 0.95v or 0.54v ddq , whichever is smaller. 21. tested initially and after any design or process change that may affect these parameters.
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 20 of 25 thermal resistance [21] parameter description test conditions 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, according to eia/jesd51. 17.2 c/w jc thermal resistance (junction to case) 3.2 c/w ac test loads and waveforms note: 22. unless otherwise noted, test conditions assume signal transition time of 2v/ns, timing reference levels of 0.75v, vref = 0.7 5v, rq = 250 ? , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads. 1.25v 0.25v r = 50 ? 5pf all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75v v ref = 0.75v [22] 0.75v under te s t 0.75v device under te s t output 0.75v v ref v ref output zq zq (a) slew rate = 2 v/ns rq = 250 ? (b) rq = 250 ?
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 21 of 25 switching characteristics over the operating range [22, 23] cypress parameter consortium parameter description 250 mhz 200 mhz 167 mhz unit min max min max min max t power v dd (typical) to the first access [26] 111ms t cyc t khkh k clock and c clock cycle time 4.0 6.3 5.0 7.9 6.0 8.4 ns t kh t khkl input clock (k/k and c/c ) high 1.6 ? 2.0 ? 2.4 ? ns t kl t klkh input clock (k/k and c/c ) low 1.6 ? 2.0 ? 2.4 ? ns t khk h t khk h k clock rise to k clock rise and c to c rise (rising edge to rising edge) 1.8 ? 2.2 ? 2.7 ? ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0.0 1.8 0.0 2.2 0.0 2.7 ns setup times t sa t avkh address setup to k clock rise 0.35 ? 0.4 ? 0.5 ? ns t sc t ivkh control setup to k clock rise (rps , wps ) 0.35 ? 0.4 ? 0.5 ? ns t scddr t ivkh double data rate control setup to clock (k, k ) rise (bws 0 , bws 1 , bws 3 , bws 4 ) 0.35 ? 0.4 ? 0.5 ? ns t sd t dvkh d [x:0] setup to clock (k/k ) rise 0.35 ? 0.4 ? 0.5 ? ns hold times t ha t khax address hold after k clock rise 0.35 ? 0.4 ? 0.5 ? ns t hc t khix control hold after k clock rise (rps , wps ) 0.35 ? 0.4 ? 0.5 ? ns t hcddr t khix double data rate control hold after clock (k, k ) rise (bws 0 , bws 1 , bws 3 , bws 4 ) 0.35 ? 0.4 ? 0.5 ? ns t hd t khdx d [x:0] hold after clock (k/k ) rise 0.35 ? 0.4 ? 0.5 ? ns output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid ?0.45?0.45?0.50ns t doh t chqx data output hold after output c/c clock rise (active to active) ?0.45 ? ?0.45 ? -0.50 ? ns t ccqo t chcqv c/c clock rise to echo clock valid ? 0.45 ? 0.45 ? 0.50 ns t cqoh t chcqx echo clock hold after c/c clock rise ?0.45 ? ?0.45 ? ?0.50 ? ns t cqd t cqhqv echo clock high to data valid ? 0.30 ? 0.35 ? 0.40 ns t cqdoh t cqhqx echo clock high to data invalid ?0.30 ? ?0.35 ? ?0.40 ? ns t chz t chqz clock (c/c ) rise to high-z (active to high-z) [24,25] ?0.45?0.45?0.50ns t clz t chqx1 clock (c/c ) rise to low-z [24,25] ?0.45 ? ?0.45 ? ?0.50 ? ns dll timing t kc var t kc var clock phase jitter ? 0.20 ? 0.20 ? 0.20 ns t kc lock t kc lock dll lock time (k, c) 1024 ? 1024 ? 1024 ? cycles t kc reset t kc reset k static to dll reset 30 ? 30 ? 30 ? ns notes: 23. all devices can operate at clock frequencie s as low as 119 mhz. when a part with a maximum frequency above 133 mhz is operat ing at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 24. t chz , t clz , are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 100 mv from steady-state voltage. 25. at any voltage and temperature t chz is less than t clz and t chz less than t co . 26. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd minimum initially before a read or write operation can be initiated. 27. for d2 data signal on CY7C1425AV18 device, t sd is 0.5 ns for 200 mhz, and 250 mhz frequencies.
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 22 of 25 switching waveforms [28, 29, 30] read/write/deselect sequence notes: 28. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, i.e., a0 + 1. 29. output are disabled (high-z) one clock cycle after a nop. 30. in this example, if address a0 = a1, then data q00 = d10 an d q01 = d11. write data is forwarded immediately as read results. this note applies to the whole diagram. k 1 2 34 5 8 10 6 7 k rps wps a d read read write write write nop read write nop 9 a0 t kh t khkh t kl t cyc tt hc t sa t ha t sd t hd sc t t sa t ha t sd t hd a6 a5 a3 a4 a1 a2 d30 d50 d51 d61 d31 d11 d10 d60 q c c dont care undefined t cq cq t khch t co t khch t clz chz t kh t kl q00 q01 q20 t khkh t cyc q21 q40 q41 t cqd t doh t ccqo t cqoh t ccqo t cqoh t cqdoh
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 23 of 25 ordering information not all of the speed, package and temperat ure ranges are available. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range 167 cy7c1410av18-167bzc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) commercial CY7C1425AV18-167bzc cy7c1412av18-167bzc cy7c1414av18-167bzc cy7c1410av18-167bzxc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free CY7C1425AV18-167bzxc cy7c1412av18-167bzxc cy7c1414av18-167bzxc cy7c1410av18-167bzi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) industrial CY7C1425AV18-167bzi cy7c1412av18-167bzi cy7c1414av18-167bzi cy7c1410av18-167bzxi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free CY7C1425AV18-167bzxi cy7c1412av18-167bzxi cy7c1414av18-167bzxi 200 cy7c1410av18-200bzc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) commercial CY7C1425AV18-200bzc cy7c1412av18-200bzc cy7c1414av18-200bzc cy7c1410av18-200bzxc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free CY7C1425AV18-200bzxc cy7c1412av18-200bzxc cy7c1414av18-200bzxc cy7c1410av18-200bzi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) industrial CY7C1425AV18-200bzi cy7c1412av18-200bzi cy7c1414av18-200bzi cy7c1410av18-200bzxi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free CY7C1425AV18-200bzxi cy7c1412av18-200bzxi cy7c1414av18-200bzxi 250 cy7c1410av18-250bzc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) commercial CY7C1425AV18-250bzc cy7c1412av18-250bzc cy7c1414av18-250bzc cy7c1410av18-250bzxc 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free CY7C1425AV18-250bzxc cy7c1412av18-250bzxc cy7c1414av18-250bzxc
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 24 of 25 ? cypress semiconductor corporation, 2004-2007. the information contained herein is subject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under pate nt or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical cont rol or safety applications, unless pursuant to an express writt en agreement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. qdr rams and quad data rate rams comprise a new family of products developed by cypress, hitachi, idt, nec, and samsung technology. all product and company names mentioned in this document are the trademarks of their respective holders. 250 cy7c1410av18-250bzi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) industrial CY7C1425AV18-250bzi cy7c1412av18-250bzi cy7c1414av18-250bzi cy7c1410av18-250bzxi 51-85195 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) pb-free CY7C1425AV18-250bzxi cy7c1412av18-250bzxi cy7c1414av18-250bzxi ordering information (continued) not all of the speed, package and temperature ranges are availabl e. please contact your local sales representative or visit www.cypress.com for actual products offered. speed (mhz) ordering code package diagram package type operating range package diagram ! 0).#/2.%2 ? ? ?8 ?-#!" ?-# " ! 8 ? -!8 3%!4).'0,!.% ? # # 0).#/2.%2 4/06)%7 "/44/-6)%7 " # $ % & ' ( * + , - . 0 2 0 2 + - . , * ( ' & % $ # " ! # 3/,$%20!$490%./.3/,$%2-!3+$%&).%$.3-$ ./4%3 0!#+!'%7%)'(4g *%$%#2%&%2%.#%-/ $%3)'.# 0!#+!'%#/$%""!$ 165-ball fbga (15 x 17 x 1.40 mm) (51-85195) 51-85195-*a
cy7c1410av18 CY7C1425AV18 cy7c1412av18 cy7c1414av18 document #: 38-05615 rev. *d page 25 of 25 document history page document title: cy7c1410av18/CY7C1425AV18/cy7c1412av1 8/cy7c1414av18 36-mbit qdr-ii? sram 2-word burst architecture document number: 38-05615 rev. ecn no. issue date orig. of change description of change ** 247331 see ecn syt new data sheet *a 326519 see ecn syt removed CY7C1425AV18 from the title included 300 mhz speed grade replaced tbds with their respective values for i dd and i sb1 added industrial temperature grade replaced the tbds on the thermal characteristics table to ja = 17.2 c/w and jc = 3.2 c/w replaced tbds in the capacitance table to their respective values for the 165 fbga package changed typo of bit # 47 to bit # 108 under the extest output bus tri-state on page 16 added pb-free product information updated the ordering information by shading and unshading mpns according to availability *b 413953 see ecn nxr converted from preliminary to final. added CY7C1425AV18 part number to title. removed 300-mhz speed bin. changed address of cypress semicond uctor corporation on page# 1 from ?3901 north first street? to ?198 champion court? changed c, c description in feature section and pin description. added power up sequence and wave form on page# 19 added foot notes # 13, 14, 15 on page# 19 replaced three-state with tri-state. changed the description of i x from input load current to input leakage current on page# 20 modified the i dd and i sb values. modified test condition in foot note # 20 on page# 20 from v ddq < v dd to v ddq < v dd. replaced package name column with package diagram in the ordering information table. updated ordering information table. *c 468029 see ecn nxr modified the zq definition from alternately, this pin can be connected directly to v dd to alternately, this pin can be connected directly to v ddq. included maximum ratings for supply voltage on v ddq relative to gnd changed the maximum ratings for dc input voltage from v ddq to v dd. changed t th and t tl from 40 ns to 20 ns, changed t tmss , t tdis , t cs , t tmsh , t tdih , t ch from 10 ns to 5 ns and changed t tdov from 20 ns to 10 ns in tap ac switching characteristics table modified power up waveform changed the maximum rating of ambient temperature with power applied from ?10c to +85c to ?55c to +125c added additional notes in the ac parameter section changed the t sc and t hc value for 250 mhz from 0.5 ns to 0.35 ns, for 200 mhz from 0.6 ns to 0.4 ns, and for 167 mhz from 0.7 ns to 0.5 ns. modified ac switching waveform. corrected the typo in the ac s witching characteristics table. updated the ordering information table. *d 1274725 see ecn vkn/aesa modified footnote# 30

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